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Design challenges in hardware development of time-sensitive networking: A research plan

Ghaderi, A.; Daneshtalab, M.; Ashjaei, M.; Loni, M.; Mubeen, S.; Sjödin, M. (2019). Design challenges in hardware development of time-sensitive networking: A research plan. CEUR Workshop Proceedings, 2457.
publitseeritud konverentsiettekanne
Ghaderi, A.; Daneshtalab, M.; Ashjaei, M.; Loni, M.; Mubeen, S.; Sjödin, M.
  • Inglise
CEUR Workshop Proceedings
CEUR Workshop Proceedings
1613-0073
2457
2019
Ilmunud
1.1. Teadusartiklid, mis on kajastatud Web of Science andmebaasides Science Citation Index Expanded, Social Sciences Citation Index, Arts & Humanities Citation Index, Emerging Sources Citation Index ja/või andmebaasis Scopus (v.a. kogumikud)
Teadmata
SCOPUS

Seotud asutused

Mälardalens högskola

Lisainfo

© 2019 CEUR-WS. All rights reserved. Time-Sensitive Networking (TSN) is a set of ongoing projects within the IEEE standardization to guarantee timeliness and low-latency communication based on switched Ethernet for industrial applications. The huge demand is mainly coming from industries where intensive data transmission is required, such as in the modern vehicles where cameras, lidars and high-bandwidth modern sensors are connected. The TSN standards are evolving over time, hence the hardware needs to change depending upon the modifications. In addition, high performance hardware is required to obtain a full benefit from the standards. In this paper, we present a research plan for developing novel techniques to support a parameterized and modular hardware IP core of the multi-stage TSN switch fabric in VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL), which can be deployed in any Field-Programmable-Gate-Array (FPGA) devices. We present the challenges on the way towards the mentioned goal.
FPGA | Memory management | Predictability | Time-sensitive network